1. Field of the Invention
The present invention relates to a phase lock loop circuit which is used in an optical repeating apparatus, and more particularly, it is an object of the present invention to provide the phase lock loop circuit which can generate a timing clock being kept almost fixed even when a space-to-mark transition-probability of an input signal changes. Further, it is another object of the present invention to provide an optical repeating apparatus, an optical terminal apparatus, and an optical communication system which use the phase lock loop circuit as mentioned above.
2. Description of the Related Art
In optical repeating apparatuses and an optical terminal apparatus which constitute an optical communication system, it is necessary to establish bit synchronization in order to reproduce respective bits of digital signals. The bit synchronization is categorized into an external-timing method and a self-timing method. The external-timing method is the method of sending timing information through a transmission line which is different from that of a main signal. The self-timing method is the method of extracting timing information from a main signal in a timing circuit. This timing circuit can be structured by using a tank circuit and a limiter, and by using a phase lock loop (hereinafter abbreviated to “PLL”) circuit.
An explanation about the structure of an optical receiving apparatus using the PLL circuit as the timing circuit will be given.
In FIG. 16, an optical signal transmitting through an optical transmission line is converted from the optical signal to an electric signal in a photoelectric conversion circuit (hereinafter abbreviated to “O/E”) 201 in the optical receiving apparatus, and the received signal whose waveform is deteriorated is compensated in an equalizing amplifier circuit (hereinafter abbreviated to “EQL”) 202. The deterioration of the waveform is caused due to transmission loss, wavelength dispersion, and a nonlinear optical effect of the optical transmission line. An output of the EQL 202 is supplied to a discrimination decision circuit (hereinafter abbreviated to “DEC”) 203 for reproducing the received signal and the timing circuit.
The timing circuit is structured by including a phase comparator 204 and a voltage controlled oscillator (hereinafter abbreviated to “VCO”, 205, and more specifically, it is structured by including a phase signal detecting circuit, a reference circuit, an amplifier, and the VCO 205.
The output of the EQL 202 is supplied to the phase signal detecting circuit and the reference circuit in the timing circuit. The phase signal detecting circuit outputs a voltage corresponding to a phase difference between the received signal and a timing clock. The reference circuit outputs a fixed voltage irrespective of the phase difference between them. This voltage value is set so that a discrimination point corresponds to the phase of the timing clock. Outputs of the phase signal detecting circuit and the reference circuit are outputted to the amplifier. The amplifier outputs a voltage based on a difference between the outputs to a control terminal of the VCO 205 for controlling its oscillation frequency. Hence, the VCO 205 oscillates so that the output of the phase signal detecting circuit corresponds to the output of the reference circuit, that is, the phase of the timing clock corresponds to the discrimination point. An output of the VCO 205 is supplied to the phase signal detecting circuit and the DEC 203.
Thus, the timing circuit generates the timing clock from the received signal. The DEC 203 discriminates whether the signal is “1” or “0” at the discrimination point given by the timing clock, thereby reproducing the received signal.
The structure of the timing circuit as such is shown in FIG. 17 in more detail.
In FIG. 17, the output of the EQL 202 is inputted to a D flip-flop circuit (hereinafter abbreviated to “D-FF”) 211 and an exclusive OR circuit (hereinafter abbreviated to “EXOR”) 212, respectively. Further, an output of the VCO 220 is inputted to a clock input of the D-FF 211.
An output of the D-FF 211 is inputted to the EXOR 212, an EXOR 216, and a delay circuit 215, respectively.
The delay circuit 215 delays the input by a half cycle and outputs it to the EXOR 216.
An output of the EXOR 212 is outputted to an amplifier (hereinafter abbreviated to “AMP”) 219 through an output part 217 and an LPF 214. The phase signal detecting circuit consists of the EXOR 212, the output part 213, and the LPF 214. Meanwhile, an output of the EXOR 216 is outputted to the AMP 219 through an output part 217 and an LPF 218. The reference circuit consists of the delay circuit 215, the EXOR 216, the output part 217, and the LPF 218. The AMP 219 outputs an output according to the outputs of the LPF 214 and the LPF 218 to a control terminal of the VCO 220.
In the timing circuit as such, when various patterns of the received signals, such as “1010” and “11001100”, are received, the outputs of the phase signal detecting circuit and the reference circuit change according to a space-to-mark transition-probability.
FIGS. 18(a) and 18(b) are time charts of the timing circuit shown in FIG. 17. FIG. 18(a) shows the case where the space-to-mark transition-probability is 1, and FIG. 18(b) shows the case where the space-to-mark transition-probability is 0.5. In FIGS. 18(a) and 18(b), the input signal in FIG. 17, the output of the VCO 220, the output of the D-FF 211, the output of the output part 213, and the output of the output part 217 are shown from the top.
When the phase of the timing clock is set as 0, the both change at the same rate, which results in that the phase of the timing clock is fixed at approximately 0 irrespective of the space-to-mark transition-probability. As a result, the discrimination point is almost fixed, and hence the received signal is reproduced at a predetermined error rate.
The space-to-mark transition-probability is the probability of the signal changing from a mark (“1”) to a space (“0”) (the probability of the signal changing from the space to the mark).
For example, when the digital signals are “11110000”, the change occurs at a rate of one bit in four bits, and hence the space-to-mark transition-probability is 0.25. When the digital signals are “11001100”, the changes occur at a rate of one bit in two bits, and hence the space-to-mark transition-probability is 0.5. When the digital signals are “10101010”, the changes occur at every bit, and hence the space-to-mark transition-probability is 1.
In order to lower the error rate, it is necessary for the discrimination point to set the phase of the timing clock other than at 0, in accordance with the state of the waveform deterioration of the received signal.
Incidentally, the state of the waveform deterioration of the received signal can be determined with reference to vertical eye opening and horizontal eye opening of an eye pattern (eye diagram).
When the discrimination point is set at the phase where the phase of the timing clock is not 0, a change ratio of the output of the phase signal detecting circuit which changes according to the space-to-mark transition-probability and a change ratio of the output of the reference circuit are different from each other in the above-described circuit. Hence, the phase of the timing clock is deviated from the set value when the space-to-mark transition-probability changes. Namely, the discrimination point changes according to the change of the space-to-mark transition-probability.
Moreover, a frequency pull-in range (capture range) of the PLL circuit is narrow. Further, even though the frequency of the optical signal (bit rate) is determined at a predetermined value, a self-oscillation frequency of the VCO fluctuates according to change of environments such as power source, temperature, and secular change. Hence, there is a possibility that the frequency of the optical signal is deviated from the frequency pull-in range of the PLL circuit. In this case, the timing clock is not generated as designed, and hence the optical receiving apparatus does not operate normally.
The EQL is structured by including, for example, a low-pass filter and a high-frequency emphasis circuit, which are connected in cascade. When the signals exceeding one gigabit are inputted to the EQL as such, it is necessary to obtain impedance matching between the low-pass filter, the high-frequency emphasis circuit and the like. However, a reflection characteristic out of a pass band of the low-pass filter such as a Bessel-Thomson filter is poor, and it is difficult to obtain the impedance matching when the circuits are connected through a wire bonding.
FIGS. 19(a) and 19(b) are views of the structure of the optical receiving apparatus in which a conventional EQL is shown in detail. FIG. 19(a) is a block diagram, and FIG. 19(b) is a schematic view showing mounting statuses of the circuits.
As shown in FIG. 19(a), a negative terminal of a power source 231 is grounded, and an output of a positive terminal thereof is inputted to an AMP 236 through a photodiode 232 as a photoreceptor, a pre-amplifier 233, a Bessel-Thomson filter 234, and a high-frequency emphasis circuit 235. An output of the AMP 236 is inputted to a timing circuit 238 and a DEC 237, the timing circuit 238 extracts a clock signal and its output is inputted to the DEC 237, and the DEC 237 reproduces the signal and outputs the reproduced signal.
Further, in FIG. 19(b), the pre-amplifier 233 and the Bessel-Thomson filter 234 are connected through wire bondings 241 as a connecting unit and microstrip lines 242 as a transmission line. The Bessel-Thomson filter 234 and the high-frequency emphasis circuit 235, and the high-frequency emphasis circuit 235 and the AMP 236 are connected similarly.